Bit Line Decoder Architecture for NOR-Type Memory Array

ABSTRACT

An integrated circuit including a plurality of bit lines, a memory array, and a bit line decoder. The memory array includes a plurality of memory cells, wherein each memory cell is respectively coupled to (i) two corresponding bit lines of the plurality of bit lines. During sensing of a state of a given memory cell, the bit line decoder (i) precharges a first bit line of the two corresponding bit lines to which the given memory cell is coupled to a first voltage potential, including precharging all other bit lines on a same side of the memory array as the first bit line to the first voltage potential, and (ii) precharges a second bit line of the two corresponding bit lines to a second voltage potential, including precharging all other bit lines on a same side of the memory array as the second bit line to the second voltage potential.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 12/231,954 (now U.S. Pat. No. 7,936,581), filed on Sep. 8, 2008, which is a continuation of U.S. patent application Ser. No. 12/127,326 (now U.S. Pat. No. 7,869,246), filed May 27, 2008, which claims the benefit of U.S. Provisional Application No. 60/940,206, filed on May 25, 2007.

TECHNICAL FIELD

The present disclosure relates to memory integrated circuits.

BACKGROUND

The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

Semiconductor memory (memory) packaged in integrated circuits (ICs) is typically organized in the form of memory arrays. Memory arrays that comprise NAND-type or NOR-type memory cells (e.g., NAND-type or NOR-type Flash memory cells) are called NAND-type or NOR-type memory arrays, respectively. Memory arrays comprise memory cells arranged in rows and columns. Memory arrays comprise decoder circuits (decoders) that select word lines (WLs) and bit lines (BLs) to read/write data in the memory cells.

Referring now to FIG. 1, an IC 10 comprising a memory array 12, a WL decoder 16, and a BL decoder 18 is shown. The memory array 12 comprises memory cells 14 arranged in rows and columns as shown. During read/write operations, depending on the address of a selected memory cell 14, the WL and BL decoders 16, 18 activate appropriate WLs and BLs, respectively, to read/write data from/to the selected memory cell 14.

Referring now to FIG. 2, an exemplary NOR-type memory array 50 utilizing a buried bit line architecture is shown. A state of an n^(th) memory cell 52 in the NOR-type memory array 50 is typically measured as follows. A WL decoder 51 selects a word line WL(n) and deselects a word line WL(n+1). A sensing circuit 54 applies a potential difference (V2−V1) across adjacent bit lines BL(n) and BL(n+1) that connect directly to the n^(th) memory cell 52. The sensing circuit 54 senses and measures a current I that flows through the n^(th) memory cell 52. A value of the current I depends on the state of the n^(th) memory cell 52. The state of the n^(th) memory cell 52 can be determined based on the value of the current I.

Typically, a pair of decoders may be used to select different pairs of adjacent bit lines that connect to different memory cells of memory arrays. The decoders may apply the potential difference (V2−V1) across the selected pairs, measure the current that flows through the selected memory cells, and determine the state of the memory cells.

Referring now to FIG. 3, an exemplary integrated circuit 70 comprising a NOR-type memory array 72, a WL decoder 74, a decoder 76, a decoder 78, and a sensing circuit 80 is shown. The decoders 76 and 78 are 1-of-N decoders, where N is an integer greater than 1 (e.g., N=8). The decoders 76 and 78 select different pairs of adjacent bit lines that connect to different memory cells of the NOR-type memory array 72. The decoders 76 and 78 apply the potential difference (V2−V1) across the memory cells connected to the selected bit lines. The sensing circuit 80 measures the current that flows through the memory cells. Thus, states of all the memory cells of the NOR-type memory array 72 can be determined.

SUMMARY

In general, in one aspect, this specification describes an integrated circuit including a plurality of bit lines, a memory array, and a bit line decoder. The memory array includes a plurality of memory cells, in which each memory cell in the memory array is respectively coupled to (i) two corresponding bit lines of the plurality of bit lines. In order to sense a state of a given memory cell of the plurality of memory cells, the bit line decoder is configured to (i) precharge a first bit line of the two corresponding bit lines to which the given memory is coupled to a first voltage potential, including precharging all other bit lines on a same side of the memory array as the first bit line to the first voltage potential, and (ii) precharge a second bit line of the two corresponding bit lines to which the given memory is coupled to a second voltage potential, including precharging all other bit lines on a same side of the memory array as the second bit line to the second voltage potential.

Further areas of applicability of the present disclosure will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:

FIG. 1 is a functional block diagram of an integrated circuit (IC) comprising a memory array according to the prior art;

FIG. 2 is a schematic of an exemplary NOR-type memory array according to the prior art;

FIG. 3 is a functional block diagram of an IC comprising a memory array, decoders, and a state sensing circuit according to the prior art;

FIG. 4 is a schematic of an exemplary NOR-type memory array;

FIG. 5A is a functional block diagram of an IC comprising a memory array, a bit line decoder decoders, and a state sensing circuit according to the present disclosure;

FIG. 5B is a schematic of an exemplary bit line decoder according to the present disclosure;

FIG. 5C is a truth table for the exemplary bit line decoder of FIG. 5B;

FIG. 6A is a schematic of an exemplary decoder tree structure of a bit line decoder according to the present disclosure;

FIG. 6B is a truth table for the exemplary bit line decoder of FIG. 6A;

FIG. 7A is a schematic of an exemplary decoder tree structure of a bit line decoder according to the present disclosure;

FIG. 7B is a schematic of an exemplary decoder tree structure of a bit line decoder according to the present disclosure;

FIG. 8 is a functional block diagram of an exemplary IC comprising a bit line decoder according to the present disclosure;

FIG. 9 is a flowchart of an exemplary method for sensing states of memory cells of memory arrays using a bit line decoder according to the present disclosure;

FIG. 10 is a flowchart of an exemplary method for sensing states of memory cells of memory arrays using a bit line decoder according to the present disclosure;

FIG. 11A is a functional block diagram of a hard disk drive;

FIG. 11B is a functional block diagram of a DVD drive;

FIG. 11C is a functional block diagram of a high definition television;

FIG. 11D. is a functional block diagram of a vehicle control system;

FIG. 11E is a functional block diagram of a cellular phone;

FIG. 11F is a functional block diagram of a set top box; and

FIG. 11G is a functional block diagram of a mobile device.

DETAILED DESCRIPTION

The following description is merely exemplary in nature and is in no way intended to limit the disclosure, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical or. It should be understood that steps within a method may be executed in different order without altering the principles of the present disclosure.

As used herein, the term module refers to an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.

Memory arrays having high storage capacities comprise a large number of memory cells and bit lines. Decoders having a tree structure (i.e., a hierarchical structure) are used to select pairs of adjacent bit lines from the large number of bit lines. The decoders select signal paths using a series of selected devices (i.e., devices that are turned on). Decoders having large tree structures, however, can be problematic for several reasons.

For example, decoders having large tree structures increase power consumption and occupy a large area of the memory integrated circuits (ICs). Additionally, when the decoders are used to measure the state of a memory cell, all bit lines other than the adjacent bit lines that connect to the memory cell are in a floating state. Furthermore, states of memory cells that are adjacent to the memory cell under measurement are unknown. Consequently, charging times to charge the adjacent bit lines to the potentials V1 and V2 are unknown. Until the adjacent bit lines are fully charged to the potentials V1 and V2, the current measured by the sensing circuit 80 is not the current that flows through the memory cell under measurement and is not representative of the state of the memory cell. Accordingly, the state of the memory cell can not be measured precisely.

Referring now to FIG. 4, the present disclosure teaches presetting the states of all the bit lines by charging the bit lines on either side of the memory cell under measurement to predetermined potentials. For example, when the state of the n^(th) memory cell 52 is measured, a WL decoder 51 selects a word line WL(n) and deselects a word line WL(n+1). Further, all the bit lines on a first side of the n^(th) memory cell 52 (i.e., BL(n), BL(n−1), etc.) can be charged to the potential V1. Additionally, all the bit lines on a second side of the n^(th) memory cell 52 (i.e., BL(n+1), BL(n+2), etc.) can be charged to the potential V2. When the state of the n^(th) memory cell 52 is measured in this manner, states of memory cells other than the n^(th) memory cell 52 are irrelevant (i.e., “don't care”).

More specifically, the present disclosure relates to a compact bit line decoder that utilizes a divisible tree structure having multiple levels. The bit line decoder comprises control devices (e.g., transistors) arranged in the multiple levels of the tree structure. The bit line decoder senses states of memory cells of memory arrays by deselecting (i.e., turning off) a predetermined number of control devices in one or more levels of the tree structure. The control devices block signal paths when deselected. When a memory cell is selected by deselecting the predetermined number of control devices, the bit line decoder presets the states of all bit lines by charging the bit lines to predetermined potentials V1 and V2 and measures the state of the memory cell.

Additionally, when memory arrays are large, the tree structure of the bit line decoder can be divided into sections. The bit line decoder can be divided into a plurality of sub-decoders by adding isolation devices between the sections. The memory arrays can be divided into memory sub-arrays, and the sub-decoders can be integrated into the memory sub-arrays.

Referring now to FIGS. 5A-5C, an IC 100 comprising an exemplary bit line decoder 102 according to the present disclosure is shown. In FIG. 5A, the IC 100 comprises the bit line decoder 102 and a NOR-type memory array 104. The bit line decoder 102 comprises a decoder tree structure 105, a control module 106, and a sensing circuit 108. The decoder tree structure 105 comprises a plurality of levels of control devices (not shown).

The control module 106 generates control signals that deselect a predetermined number of control devices in each level of the decoder tree structure 105. The predetermined number depends on the decoder tree structure (e.g., number of levels in the decoder tree structure). The control signals may include address lines used to address the memory cells of the NOR-type memory array 104. The bit line decoder 102 senses states of the memory cells of the NOR-type memory array 104 based on the control signals as follows.

In FIG. 5B, as an example, the decoder tree structure 105 is shown to comprise a binary tree structure 110. The binary tree structure 110 may have L levels when the bit line decoder 102 measures states of 2^(L) memory cells of the NOR-type memory array 104, where L is an integer greater than or equal to 1. A level L includes 2^(L) control devices. The control devices may include transistors. A level adjacent or closest to the NOR-type memory array 104 is called a lowest level of the binary tree structure 110. A level farthest from the NOR-type memory array 104 is called a highest level of the binary tree structure 110. The lowest level includes the most number of control devices. The highest level includes the least number of control devices.

As an example, the NOR-type memory array 104 is shown to comprise a group of 8 memory cells (not shown) and 8 bit lines for simplicity. Since 2^(L)=8 gives L=3, the bit line decoder 102 that measures states of the 8 memory cells of the NOR-type memory array 104 has a 3-level decoder tree structure. Accordingly, the bit line decoder 102 may be called a 3-level decoder. The lowest level (L=3) includes 2³=8 control devices. The 8 control devices are organized into 4 groups. Each of the 4 groups comprises 2 control devices. The highest level (L=1) includes 2¹=2 control devices.

In use, the control module 106 generates control signals that deselect or turn off one of every two control devices at each level of the binary tree structure 110. The control signals may include address lines used to address memory cells of the NOR-type memory array 104. The deselected control devices are marked “X” in FIG. 5B. Based on the control signals and the control devices deselected by the control signals, a memory cell connected to a pair of adjacent bit lines is selected for measurement. A truth table for the binary tree structure 110 is shown in FIG. 5C.

As shown in the truth table, when the control signals are C2=C1=C0=0, based on the control devices deselected by the control signals, the memory cell connected to bit lines BL0 and BL1 is selected. The state of the selected memory cell is measured by applying voltage V1 to bit line BL0 and voltage V2 to the bit lines BL1-BL7. When the control signals are C2=C1=0 and C0=1, based on the control devices deselected by the control signals, the memory cell connected to bit lines BL1 and BL2 is selected. The state of the selected memory cell is measured by applying voltage V1 to bit lines BL0-BL1 and voltage V2 to the bit lines BL2-BL7. When the control signals are C2=C0=0 and C1=1, based on the control devices deselected by the control signals, the memory cell connected to bit lines BL2 and BL3 is selected. The state of the selected memory cell is measured by applying voltage V1 to bit lines BL0-BL2 and voltage V2 to the bit lines BL3-BL7, and so on.

In the example shown in FIG. 5B, based on the deselected devices, a memory cell connected to the bit lines BL3 and BL4 is selected for measurement. Although the truth table shown uses the control signals C0-C2, control signals C0B-C2B, which are inverted control signals C0-C2, may be alternatively used. The bit line decoder 102 measures the state of the memory cell as follows.

A sensing circuit 108 applies the potential V1 to the bit lines BL3-BL0 and the potential V2 to the bit lines BL4-BL8. The sensing circuit 108 measures the current that flows through the memory cell and measures the state of the memory cell based on the current. For example, the current may have a first value when the memory cell is in a first state and a second value when the memory cell is in a second state. The first state and the first value may be different than the second state and the second value, respectively.

Referring now to FIGS. 6A and 6B, bit line decoders may have tree structures that are different than binary tree structures. In FIG. 6A, as an example, the decoder tree structure 150 may comprise a 2-level decoder tree structure 150 that is used to measure states of the 8 memory cells of the NOR-type memory array 104. A lower level (L=2) of the decoder tree structure 150 that connects to the NOR-type memory array 104 comprises 8 control devices. The 8 control devices are organized into 2 groups. Each of the 2 groups comprises 4 control devices. An upper level (L=1) comprises 2 control devices.

In general, the lower level (L=2) of the decoder tree structure 150 may comprise C control devices, where log₂C is an integer greater than 2, and the C control devices communicate with (C+1) bit lines. The C control devices may be organized in two groups, and one control device in each group may be deselected.

In use, the control module 106 generates control signals that deselect one of every four control devices in the lower level of the decoder tree structure 150. The deselected control devices are marked “X” in FIG. 6A. Based on the control signals and the control devices deselected by the control signals, a memory cell connected to a pair of adjacent bit lines is selected for measurement. A truth table for the 2-level decoder tree structure 150 is shown in FIG. 6B.

As shown in the truth table, when the control signals are C2=0, C03=C02=C01=1, and C00=0, based on the control devices deselected by the control signals, the memory cell connected to bit lines BL0 and BL1 is selected. The state of the selected memory cell is measured by applying voltage V1 to bit line BL0 and voltage V2 to the bit lines BL1-BL8. When the control signals are C2=0, C03=C02=C00=1, and C01=0, based on the control devices deselected by the control signals, the memory cell connected to bit lines BL1 and BL2 is selected. The state of the selected memory cell is measured by applying voltage V1 to bit lines BL0-BL1 and voltage V2 to the bit lines BL2-BL8. When the control signals are C2=0, C03=C01=C00=1, and C02=0, based on the control devices deselected by the control signals, the memory cell connected to bit lines BL2 and BL3 is selected. The state of the selected memory cell is measured by applying voltage V1 to bit lines BL0-BL2 and voltage V2 to the bit lines BL3-BL8, etc.

In the example shown in FIG. 6A, based on the deselected devices, a memory cell connected to the bit lines BL3 and BL4 is selected for measurement. The sensing circuit 108 applies the potential V1 to the bit lines BL3-BL0 and the potential V2 to the bit lines BL4-BL8. The sensing circuit 108 measures the current that flows through the memory cell and measures the state of the memory cell based on the current.

When the storage capacity of NOR-type memory arrays is large, the number of bit lines can be very large (e.g., 128 bit lines per bit line group). When the sensing circuit 108 charges a large number of bit lines to the predetermined potentials, the capacitances of the bit lines add up to a net capacitance. The value of the net capacitance can be very high. The high value of the net capacitance decreases the sensing speed of the sensing circuit 108.

The value of the net capacitance can be decreased and the sensing speed can be increased by segmenting the NOR-type memory arrays into a plurality of memory sub-arrays. Additionally, bit line decoders may be divided into a plurality of sub-decoders at any level of the decoder tree structure. Isolation devices may be provided between the sub-decoders of adjacent levels. Each of the memory sub-arrays communicates with a sub-decoder comprising one or more lower tree-levels of the decoder tree structure. When the state of a memory cell of a memory sub-array is measured, only the memory sub-array that includes the memory cell under measurement is connected to the sensing circuit.

Referring now to FIGS. 7A and 7B, exemplary decoder tree structures 160 and 161 that are divided into two sub-decoders are shown, respectively. The two sub-decoders are called a lower-tree sub-decoder and an upper-tree sub-decoder. An isolation circuit 192 comprising isolating devices (e.g., transistors) separates (i.e., isolates) the lower-tree sub-decoder from the upper-tree sub-decoder as shown.

The control module 106 generates control signals that are input to the isolating devices. Based on the control signals, the isolation circuit 192 isolates the lower-tree sub-decoder from the upper-tree sub-decoder. When the lower-tree sub-decoder is isolated from the upper-tree sub-decoder, the sensing circuit 108 cannot sense the state of any memory cell of a memory sub-array that communicates with the lower-tree sub-decoder. On the other hand, based on the control signals, when the isolation circuit 192 does not isolate the lower-tree sub-decoder from the upper-tree sub-decoder, the sensing circuit 108 measures the state of a memory cell of the memory sub-array that communicates with the lower-tree sub-decoder.

In some implementations, the lower-tree sub-decoder and/or the upper-tree sub-decoder of the decoder tree structure 160 may comprise a plurality of levels of the decoder tree structure 160. Alternatively, the lower-tree sub-decoder and the upper-tree sub-decoder of the decoder tree structure 161 may comprise the lower level (L=2) and the upper level (L=1) of the decoder tree structure 161, respectively.

Referring now to FIG. 8, an IC 180 comprising a memory array 182 and a bit line decoder 184 is shown. The memory array 182 is segmented into a plurality of memory sub-arrays 182-1, 182-2, . . . , and 182-N (collectively memory sub-arrays 182), where N is an integer greater than 1. The bit line decoder 184 comprises a control module 186, the sensing circuit 108, the isolation circuits 192, and a divided decoder tree structure.

Specifically, the divided decoder tree structure of the bit line decoder 184 is divided into an upper-tree sub-decoder 190 and a plurality of lower-tree sub-decoders 188-1 188-2, . . . , and 188-N (collectively lower-tree sub-decoders 188). The lower-tree sub-decoders 188 are separated (i.e., isolated) from the upper-tree sub-decoder 190 by isolation circuits 192-1, 192-2, . . . , and 192-N (collectively isolation circuits 192), respectively.

Each isolation circuit 192 may include a plurality of isolation devices (e.g., transistors). The outputs of the isolation devices of one isolation circuit 192 are connected to the corresponding outputs of the isolation devices of the other isolation circuits 192 to form global bit lines as shown. The global bit lines connect to the upper-tree sub-decoder 190.

The sensing circuit 108 uses the global bit lines to communicate with the memory sub-arrays 182. The sensing circuit 108 communicates with one of the memory sub-arrays 182 at a time. The sensing circuit 108 does not communicate with more than one of the memory sub-arrays 182 at a time.

In use, the control module 186 generates first control signals that deselect a predetermined number of control devices at each tree-level of the lower-tree sub-decoders 188 and the upper-tree sub-decoder 190. The predetermined number is based on the tree structure of the bit line decoder 184 and the number of levels in the decoder tree structure. Based on the first control signals and the deselected control devices, a memory cell of one of the memory sub-arrays 182 is selected for measurement. For example, the memory cell under measurement may be located in the memory sub-array 182-k, where 1≦k≦N. The first control signals may include the address lines used to address the memory cells in the NOR-type memory array 182.

Additionally, the control module 186 generates second control signals that control the isolation circuits 192. Specifically, when the memory cell under measurement is located in the memory sub-array 182-k, the second control signals select the isolation circuit 192-k. Accordingly, when the sensing circuit 108 measures the state of the memory cell of the memory sub-array 182-k, only the bit lines of the memory sub-array 182-k are charged to the predetermined potentials V1 and V2. The sensing circuit 108 communicates with the memory sub-array 182-k via the global bit lines and the selected isolation circuit 192-k.

Specifically, the sensing circuit 108 applies the potential difference (V2−V1) across the adjacent bit lines that connect to the memory cell under measurement in the memory sub-array 182-k. Additionally, in the memory sub-array 182-k, all the bit lines on the first side of the memory cell are charged to the potential V1, and all the bit lines on the second side of the memory cell are charged to the potential V2. The sensing circuit 108 measures the current that flows through the memory cell and determines the state of the memory cell.

Referring now to FIG. 9, a method 200 for measuring the state of the memory cell of the NOR-type memory array 104 using the bit line decoder 102 begins at step 202. The control module 106 selects bit lines adjacent to the memory cell under measurement by deselecting a predetermined number of control devices in each level of the bit line decoder 102 in step 204. The sensing circuit 108 charges all the bit lines on the first side of the memory cell to the potential V1 in step 206. The sensing circuit 108 charges all the bit lines on the second side of the memory cell to the potential V2 in step 208. The sensing circuit 108 measures the current that flows through the memory cell in step 210. The sensing circuit 108 determines the state of the memory cell based on the current in step 212. The method ends in step 214.

Referring now to FIG. 10, a method 250 for measuring the state of the memory cell of the NOR-type memory array 182 using the bit line decoder 184 begins at step 252. The memory array 182 is segmented into memory sub-arrays 182-1, 182, . . . , and 182-N in step 254. The bit line decoder 184 is divided into the upper-tree sub-decoder 190 and the lower-tree sub-decoders 188 in step 256. Each memory sub-array 182-k is connected to one lower-tree sub-decoder 188-k in step 258. In step 260, each lower-tree sub-decoder 188-k is separated (i.e., isolated) from the upper-tree-sub-decoder 190 by isolation circuits 192-k. Outputs of the isolation circuits 192 are connected together in step 262 to form global bit lines that connect to the upper-tree sub-decoder 190.

In step 264, the control module 186 selects the isolation circuit 192-k that connects to the memory array 182-k where the memory cell under measurement is located. In step 266, the control module 186 selects the bit lines adjacent to the memory cell by deselecting a predetermined number of control devices in each level of the lower-tree sub-decoder 188-k and the upper-tree sub-decoder 190.

The sensing circuit 108 charges all the bit lines on the first side of the memory cell in the memory sub-array 182-k to the potential V1 in step 268. The sensing circuit 108 charges all the bit lines on the second side of the memory cell in the memory sub-array 182-k to the potential V2 in step 270. The sensing circuit 108 measures the current that flows through the memory cell in step 272. The sensing circuit 108 determines the state of the memory cell based on the current in step 274. The method 250 ends in step 276.

Referring now to FIGS. 11A-11G, various exemplary implementations incorporating the teachings of the present disclosure are shown.

In FIG. 11A, the teachings of the disclosure can be implemented in nonvolatile memory 312 of a hard disk drive (HDD) 300. The HDD 300 includes a hard disk assembly (HDA) 301 and an HDD printed circuit board (PCB) 302. The HDA 301 may include a magnetic medium 303, such as one or more platters that store data, and a read/write device 304. The read/write device 304 may be arranged on an actuator arm 305 and may read and write data on the magnetic medium 303. Additionally, the HDA 301 includes a spindle motor 306 that rotates the magnetic medium 303 and a voice-coil motor (VCM) 307 that actuates the actuator arm 305. A preamplifier device 308 amplifies signals generated by the read/write device 304 during read operations and provides signals to the read/write device 304 during write operations.

The HDD PCB 302 includes a read/write channel module (hereinafter, “read channel”) 309, a hard disk controller (HDC) module 310, a buffer 311, nonvolatile memory 312, a processor 313, and a spindle/VCM driver module 314. The read channel 309 processes data received from and transmitted to the preamplifier device 308. The HDC module 310 controls components of the HDA 301 and communicates with an external device (not shown) via an I/O interface 315. The external device may include a computer, a multimedia device, a mobile computing device, etc. The I/O interface 315 may include wireline and/or wireless communication links.

The HDC module 310 may receive data from the HDA 301, the read channel 309, the buffer 311, nonvolatile memory 312, the processor 313, the spindle/VCM driver module 314, and/or the I/O interface 315. The processor 313 may process the data, including encoding, decoding, filtering, and/or formatting. The processed data may be output to the HDA 301, the read channel 309, the buffer 311, nonvolatile memory 312, the processor 313, the spindle/VCM driver module 314, and/or the I/O interface 315.

The HDC module 310 may use the buffer 311 and/or nonvolatile memory 312 to store data related to the control and operation of the HDD 300. The buffer 311 may include DRAM, SDRAM, etc. Nonvolatile memory 312 may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The spindle/VCM driver module 314 controls the spindle motor 306 and the VCM 307. The HDD PCB 302 includes a power supply 316 that provides power to the components of the HDD 300.

In FIG. 11B, the teachings of the disclosure can be implemented in nonvolatile memory 323 of a DVD drive 318 or of a CD drive (not shown). The DVD drive 318 includes a DVD PCB 319 and a DVD assembly (DVDA) 320. The DVD PCB 319 includes a DVD control module 321, a buffer 322, nonvolatile memory 323, a processor 324, a spindle/FM (feed motor) driver module 325, an analog front-end module 326, a write strategy module 327, and a DSP module 328.

The DVD control module 321 controls components of the DVDA 320 and communicates with an external device (not shown) via an I/O interface 329. The external device may include a computer, a multimedia device, a mobile computing device, etc. The I/O interface 329 may include wireline and/or wireless communication links.

The DVD control module 321 may receive data from the buffer 322, nonvolatile memory 323, the processor 324, the spindle/FM driver module 325, the analog front-end module 326, the write strategy module 327, the DSP module 328, and/or the I/O interface 329. The processor 324 may process the data, including encoding, decoding, filtering, and/or formatting. The DSP module 328 performs signal processing, such as video and/or audio coding/decoding. The processed data may be output to the buffer 322, nonvolatile memory 323, the processor 324, the spindle/FM driver module 325, the analog front-end module 326, the write strategy module 327, the DSP module 328, and/or the I/O interface 329.

The DVD control module 321 may use the buffer 322 and/or nonvolatile memory 323 to store data related to the control and operation of the DVD drive 318. The buffer 322 may include DRAM, SDRAM, etc. Nonvolatile memory 323 may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The DVD PCB 319 includes a power supply 330 that provides power to the components of the DVD drive 318.

The DVDA 320 may include a preamplifier device 331, a laser driver 332, and an optical device 333, which may be an optical read/write (ORW) device or an optical read-only (OR) device. A spindle motor 334 rotates an optical storage medium 335, and a feed motor 336 actuates the optical device 333 relative to the optical storage medium 335.

When reading data from the optical storage medium 335, the laser driver provides a read power to the optical device 333. The optical device 333 detects data from the optical storage medium 335, and transmits the data to the preamplifier device 331. The analog front-end module 326 receives data from the preamplifier device 331 and performs such functions as filtering and A/D conversion. To write to the optical storage medium 335, the write strategy module 327 transmits power level and timing data to the laser driver 332. The laser driver 332 controls the optical device 333 to write data to the optical storage medium 335.

In FIG. 11C, the teachings of the disclosure can be implemented in memory 341 of a high definition television (HDTV) 337. The HDTV 337 includes an HDTV control module 338, a display 339, a power supply 340, memory 341, a storage device 342, a network interface 343, and an external interface 345. If the network interface 343 includes a wireless local area network interface, an antenna (not shown) may be included.

The HDTV 337 can receive input signals from the network interface 343 and/or the external interface 345, which can send and receive data via cable, broadband Internet, and/or satellite. The HDTV control module 338 may process the input signals, including encoding, decoding, filtering, and/or formatting, and generate output signals. The output signals may be communicated to one or more of the display 339, memory 341, the storage device 342, the network interface 343, and the external interface 345.

Memory 341 may include random access memory (RAM) and/or nonvolatile memory. Nonvolatile memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The storage device 342 may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD). The HDTV control module 338 communicates externally via the network interface 343 and/or the external interface 345. The power supply 340 provides power to the components of the HDTV 337.

In FIG. 11D, the teachings of the disclosure may be implemented in memory 349 of a vehicle 346. The vehicle 346 may include a vehicle control system 347, a power supply 348, memory 349, a storage device 350, and a network interface 352. If the network interface 352 includes a wireless local area network interface, an antenna (not shown) may be included. The vehicle control system 347 may be a powertrain control system, a body control system, an entertainment control system, an anti-lock braking system (ABS), a navigation system, a telematics system, a lane departure system, an adaptive cruise control system, etc.

The vehicle control system 347 may communicate with one or more sensors 354 and generate one or more output signals 356. The sensors 354 may include temperature sensors, acceleration sensors, pressure sensors, rotational sensors, airflow sensors, etc. The output signals 356 may control engine operating parameters, transmission operating parameters, suspension parameters, etc.

The power supply 348 provides power to the components of the vehicle 346. The vehicle control system 347 may store data in memory 349 and/or the storage device 350. Memory 349 may include random access memory (RAM) and/or nonvolatile memory. Nonvolatile memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The storage device 350 may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD). The vehicle control system 347 may communicate externally using the network interface 352.

In FIG. 11E, the teachings of the disclosure can be implemented in memory 364 of a cellular phone 358. The cellular phone 358 includes a phone control module 360, a power supply 362, memory 364, a storage device 366, and a cellular network interface 367. The cellular phone 358 may include a network interface 368, a microphone 370, an audio output 372 such as a speaker and/or output jack, a display 374, and a user input device 376 such as a keypad and/or pointing device. If the network interface 368 includes a wireless local area network interface, an antenna (not shown) may be included.

The phone control module 360 may receive input signals from the cellular network interface 367, the network interface 368, the microphone 370, and/or the user input device 376. The phone control module 360 may process signals, including encoding, decoding, filtering, and/or formatting, and generate output signals. The output signals may be communicated to one or more of memory 364, the storage device 366, the cellular network interface 367, the network interface 368, and the audio output 372.

Memory 364 may include random access memory (RAM) and/or nonvolatile memory. Nonvolatile memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The storage device 366 may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD). The power supply 362 provides power to the components of the cellular phone 358.

In FIG. 11F, the teachings of the disclosure can be implemented in memory 383 of a set top box 378. The set top box 378 includes a set top control module 380, a display 381, a power supply 382, memory 383, a storage device 384, and a network interface 385. If the network interface 385 includes a wireless local area network interface, an antenna (not shown) may be included.

The set top control module 380 may receive input signals from the network interface 385 and an external interface 387, which can send and receive data via cable, broadband Internet, and/or satellite. The set top control module 380 may process signals, including encoding, decoding, filtering, and/or formatting, and generate output signals. The output signals may include audio and/or video signals in standard and/or high definition formats. The output signals may be communicated to the network interface 385 and/or to the display 381. The display 381 may include a television, a projector, and/or a monitor.

The power supply 382 provides power to the components of the set top box 378. Memory 383 may include random access memory (RAM) and/or nonvolatile memory. Nonvolatile memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The storage device 384 may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD).

In FIG. 11G, the teachings of the disclosure can be implemented in memory 392 of a mobile device 389. The mobile device 389 may include a mobile device control module 390, a power supply 391, memory 392, a storage device 393, a network interface 394, and an external interface 399. If the network interface 394 includes a wireless local area network interface, an antenna (not shown) may be included.

The mobile device control module 390 may receive input signals from the network interface 394 and/or the external interface 399. The external interface 399 may include USB, infrared, and/or Ethernet. The input signals may include compressed audio and/or video, and may be compliant with the MP3 format. Additionally, the mobile device control module 390 may receive input from a user input 396 such as a keypad, touchpad, or individual buttons. The mobile device control module 390 may process input signals, including encoding, decoding, filtering, and/or formatting, and generate output signals.

The mobile device control module 390 may output audio signals to an audio output 397 and video signals to a display 398. The audio output 397 may include a speaker and/or an output jack. The display 398 may present a graphical user interface, which may include menus, icons, etc. The power supply 391 provides power to the components of the mobile device 389. Memory 392 may include random access memory (RAM) and/or nonvolatile memory.

Nonvolatile memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The storage device 393 may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD). The mobile device may include a personal digital assistant, a media player, a laptop computer, a gaming console, or other mobile computing device.

Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification, and the following claims. 

1. An integrated circuit comprising: a plurality of bit lines; a plurality of word lines; a memory array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns, wherein each memory cell in the memory array is respectively coupled to (i) two corresponding bit lines of the plurality of bit lines, and (ii) a corresponding word line of the plurality of word lines; and a bit line decoder in communication with the plurality of bit lines; and a word line decoder in communication with the plurality of word lines, wherein during sensing of a state of a given memory cell of the plurality of memory cells, the word line decoder is configured to activate only the word line corresponding to the given memory cell, and the bit line decoder is configured to precharge a first bit line of the two corresponding bit lines to which the given memory cell is coupled to a first voltage potential, including precharging all other bit lines on a same side of the memory array as the first bit line to the first voltage potential, and precharge a second bit line of the two corresponding bit lines to which the given memory cell is coupled to a second voltage potential, including precharging all other bit lines on a same side of the memory array as the second bit line to the second voltage potential.
 2. The integrated circuit of claim 1, further comprising a sensing circuit operable to sense the state of the given memory cell.
 3. The integrated circuit of claim 1, wherein each memory cell in the memory array comprises a NOR-type memory array.
 4. The integrated circuit of claim 1, wherein each memory cell in the memory array comprises a NAND-type memory array.
 5. A device comprising the integrated circuit of claim
 1. 6. The device of claim 5, wherein the device is a device selected from the group consisting of: a hard disk drive, a DVD drive, a high definition television, a vehicle control system, a cellular phone, and a set top box. 